1. Field of the Invention
This invention relates to a scan test circuit and a semiconductor integrated circuit device using the same. More particularly, the invention relates to a scan test circuit including a scan register to be incorporated in a semiconductor integrated circuit device for testing the latter, and it also relates to a semiconductor integrated circuit device using the same.
2. Description of the Background Art
With the progress of the minute processing technique, the degree of integration of semiconductor integrated circuits has surprisingly increased and tends to continue to further increase after this. With such increase in the degree of integration (the number of gates), the difficulty involved in testing semiconductor integrated circuits has exponentially increased. The degree of ease of testing a device is determined by two points, the ease with which the faults of terminals are observed (observability) and the ease with which terminals are set at desired logic values (controllability). Generally, the deep terminals of a large scale logic network become worse both in observability and controllability.
Methods for testing semiconductor integrated circuit devices include one method called a scan test. In this scan test, register circuits having the shift register function are inserted in suitable places in a logic network, and are connected to a single shift register path. During test, a test pattern is serially inputted from outside the chip and predetermined data are set in the registers. A logic circuit is connected to the data output terminal of each register, and a desired logic signal is inputted to the logic circuit. Each logic circuit operates in response to its logic signal, and the result is fed in parallel into the register through the parallel input terminal of the register. Thereafter, the data set in the register are serially outputted outside the chip, and observation of the output makes it possible to improve the observability and controllability of the deep terminals of a large scale logic network.
Further, scan test circuits directed to asynchronous sequential circuits are disclosed in Japanese Patent
Laid-Open Nos. 74668/1981, 38179/1988 and 38184/1988. The prior art disclosed in Japanese Patent Application No. 38184/1988 will now be described.
FIG. 16 is a block diagram showing an example of a conventional scan test circuit for making scan tests. Referring to FIG. 16, the scan test circuit SRL includes latch circuits L1, L2 and L3 and inverters 1 through 4. Serial data are inputted to the inverter 1 from a second input terminal SI. The output of the inverter 1 is given to the latch circuit L1. The latch circuit L1 comprises inverters 5 and 6 and transfer gates 13 and 15 in the form of n MOS transistors. The input of the inverter 5 is connected to the output of the inverter 6, while the output of the inverter 5 is connected to the input of the inverter 6, thereby forming a register.
A transfer gate 13 is connected between the input of the inverter 5 and the output of the inverter 2. The inverter 2 has data inputted thereto from a first input terminal D1. The gate of the transfer gate 13 is given a clock signal from an input terminal TD. A transfer gate 15 is connected between the input of the inverter 5 and the output of the inverter 1, and the gate of the transfer gate 15 is given the clock signal through an input terminal T1. The output of the latch circuit L1 is given to the latch circuits L2 and L3. The latch circuit L2 comprises inverters 7 and 8 and a transfer gate 19. The input of the inverter 7 is connected to the output of the inverter 8, while the output of the inverter 7 is connected to the input of the inverter 8, thereby forming a register. A transfer gate 19 is connected between the input of the inverter 7 and the output of the latch circuit L1, and the gate of the transfer gate 19 is given the clock signal from the input terminal T2. The output signal from the latch circuit L2 is given to the second output terminal SO through the inverter 4.
The latch circuit L3 comprises inverters 9 and 10 and a transfer gate 17. The input of the inverter 9 is connected to the output of the inverter 10, while the output of the inverter 9 is connected to the input of the inverter 10, thereby forming a register. The transfer gate 17 is connected between the input of the inverter 9 and the latch circuit L1, and the gate of the transfer gate 17 is given the clock signal from the input terminal L3. The output signal from the latch circuit L3 is outputted to the first output terminal DO through the inverter 3.
FIG. 17 is a block diagram showing a semiconductor integrated circuit chip provided with the scan test circuit shown in FIG. 16. Referring to FIG. 17, the single chip contains circuit blocks CB1 and CB2 to be tested. The output terminals DO of the scan test circuits SRL1 and SRL2 are connected to the input terminals Il and I2 of the circuit block CB1, respectively. The input terminals DI of the scan test circuits SRL3 and SRL4 are connected to the output terminal 01 of the circuit block CB1, while the output terminals DO of the scan test circuits SRL3 and SRL4 are connected to the input terminals I1 and I2 of the circuit block CB2.
The input terminals DI of the scan test circuits SRL5 and SRL6 are connected to the output terminals 01 and 02 of the circuit block CB2. Scan test circuits SRL1 through SRL6 are connected between the serial data input terminal SI, and the serial data output terminal SO, of the chip, thereby forming a scan path. The input terminal T3 of the scan test circuit SRL1 is connected to the clock input terminal T3a of the chip. The input terminals T3 of the scan test circuits SRL2, SRL3 and SRL4 are connected to the input terminal T3b of the chip and are given the clock signal. The input terminals TD of the scan test circuits SRL3 through SRL6 are connected to the input terminal TD of the chip and are given the clock signal.
FIG. 18 is a flowchart for explaining the operation for testing the circuit block shown in FIG. 17, and FIG. 19 is a timing chart.
Referring to FIGS. 16 and 19, the operation of a conventional scan test circuit will now be described. The circuit block is divided into two parts, one for normal operation and the other for test operation. During normal operation, signals given to the test input terminals T1 and T2 of the chip are set at "L" level, and signals given to the input terminals TD, T3a and T3b are set at "H" level. With signals thus set, in the scan test circuit SRL shown in FIG. 16, the transfer gates 13 and 17 are rendered conductive, while the transfer gates 15 and 19 are rendered nonconductive. Thereby, the latch circuit L1 becomes a through-circuit by which data inputted from the input terminal DI through the inverter 2 are passed through, and the latch circuit L3 also acts as a through-circuit by which data inputted from the latch circuit L1 are passed through to the inverter 3.
On the other hand, the latch circuit L2 is in the data holding state since the transfer gate 19 is held nonconductive. Therefore, the scan test circuits SRL shown in FIG. 16 are inhibited from receiving data from the serial data input terminals SI; therefore, the path from the input terminal DI to the output terminal DO acts simply as a data transfer circuit. Thus, since the path from the input terminal DI to the output terminal DO in the scan test circuit SRL between the circuit blocks CB1 and CB2 assumes the data-through state, the line between the circuit blocks CB1 and CB2 assumes the logically conductive state, performing the same logic function as before the scan test circuits SRL1 through SRL6 are inserted.
The test operation will now be described. The test operation is divided into two modes: a scan operation mode and a block test operation mode. In the scan operation mode, test patterns for the circuit blocks CB1 and CB2 to be tested are serially inputted from the serial data input terminals SI and, simultaneously, output data from the circuit blocks CB1 and CB2 to be tested are serially outputted from the serial data terminals SO. And in the block test operation mode, test patterns for the circuit block CB1 and CB2 to be tested which are inputted to the scan test circuits SRL1 through SRL6 are synchronized with clock signals given to the input terminals T3a and T3b and inputted to the input terminals of the circuit blocks CB1 and CB2 to be actually tested. Then, test data are held in the latch circuit L1 within the corresponding scan test circuit SRL synchronized with the response waveform. The scan operation mode and block test mode are alternately repeated for each pattern in the circuit block to be tested, whereby the scan test of the circuit block to be tested is achieved. Further, the test of the chip is achieved by repeating the processing in this procedure the same number of times as the number of circuit blocks to be tested existing in the chip.
The test operation will be further described with the chip shown in FIG. 17 taken as an example. This chip includes circuit blocks CB1 and CB2, and by testing the circuit blocks CB1 and CB2, the test of the chip can be achieved. The test patterns necessary for the test of the circuit blocks CB1 and CB2 are shown in Tables 1A and 1B, respectively.
TABLE 1B ______________________________________ CBI Test Patterns Input Output I1 I2 O1 ______________________________________ 1 H H H 2 H L L 3 L L H 4 L H H ______________________________________
TABLE 1A ______________________________________ CB2 Test Patterns Input Output I1 I2 O1 O2 ______________________________________ 1 L L H L 2 H L H H 3 L H H H 4 H H L H ______________________________________
As shown in Table 1A, four patterns are required as test patterns for the circuit block CB1. For example, if the input terminals Il and I2 of the circuit block CB1 are given "H", "H" level signals with desired timing, an output signal at "H" level is given from the output terminal 01 of the circuit block CB1. Similarly, for "H", "L" signals, there is obtained an output signal at "L" level; and for "L", "H" signals, there is obtained an output signal at "H" level. Similarly, the circuit block CB2 can be tested by observing the output patterns associated with the input patterns.
These test patterns are serially inputted to the serial data input terminal SI' and transferred on the scan path, and input data are set ion a desired scan test circuit SRL. Further, in order to serially output the test patterns shown in Tables 1A and 1B have to be converted into serial data. Test patterns are converted into such serial data are shown in Tables 2A and 2B.
TABLE 2A TABLE 2B ______________________________________ Chip Test Patterns (Scan Path Input/Output Serial Data) SCAN Input Pattern Output Pattern ______________________________________ #1 XXXXHH XXXXXX 2 XXXXLH CB1 XXHHXX 3 XXXXLL test XXLLXX 4 XXXXHL XXHHXX 5 XXLLXX XXHHXX 6 XXHLXX LHXXXX 7 XXLHXX CB2 HHXXXX 8 XXHHXX test HHXXXX 9 XXXXXX HLXXXX ______________________________________
Table 2A shows test input patterns inputted from the serial data input terminal SI', while Table 2B shows test output patterns outputted from the serial data output terminal SO'. In FIG. 17, six scan test circuits SRL1 through SRL6 are connected on the scan path extending from the serial data input terminal SI' to the serial data output terminal SO'; therefore, an amount of clock signal corresponding to periods is required for each scan operation. In Tables 2A and 2B, the mark X indicates dummy data required during scan shift, said dummy data being required when test input data from the serial data input terminal are set in a predetermined scan test circuit SRL to provide the shift necessary for outputting the test output data from the predetermined scan test circuit SRL to the scan data output terminal SO'.
The number of test patterns necessary for testing the circuit block CB1 is four, and also four test patterns are required for testing the circuit block CB2. Further, as is clear from the flow chart showing in FIG. 18, one pattern is required for outputting the test output data from the serial data output terminal SO after completion of the test operation of the circuit block CB2. Therefore, a total of nine patterns are used to complete the test of the chip. The serially converted data are serially inputted from the serial data input terminal SI' in the scan mode. During test operation, the blocks are tested by repetitively performing the scan mode and the test mode.
FIG. 19 is a timing chart showing the timing for the parts shown in FIG. 18. The scan mode will now be described in more detail with reference to FIG. 19. As shown in FIG. 19 (g), a clock signal at "L" level is given to the input terminal TD. As shown in FIG. 19 (c) and (d), the input terminals T1 and T2 are given scan clock signals as non-overlapping, positive clock signals. Synchronously therewith, data from the scan data input terminal SI' are successively "scanned in" to the scan test circuits SRL1 through SRL6. An amount of scan signal corresponding to six periods is required to input desired data to a predetermined scan test circuit SRL. At the same time, as shown in FIG. 19 (b), the output data from the circuit block CB1 or CB2 taken into the predetermined scan test circuit in the preceding test (in the example shown in FIG. 17, the scan test circuit SRL3, SRL4 or SRL5, SRL6) are successively scanned out.
The test mode will now be described. When desired test input data are set in a predetermined scan test circuit SRL, a single positive clock pulse shown in FIG. (e) and (f) is given to the input terminals T3a and T3b . Thereby, the test input data are latched in the third latch circuit L3 of the scan test SRL and is given to the circuit block CB1. At the time when the respective operations of the circuit blocks CB1 and CB2 are completed, a positive clock pulse is given to the input terminal TD as the data clock signal shown in FIG. 19 (g). Thereby, the output signal from each circuit block is latched in the first latch circuit L1 of the corresponding scan circuit SRL through the input terminal DI of the scan test circuit SRL.
Subsequently, a single positive clock pulse is given to the input terminal T2 as a second scan clock signal, whereby the output signal from the circuit block is retained in the second latch circuit L2 of the scan test circuit SRL. Thereafter, the mode is changed to the scan mode and the test proceeds.
The circuit blocks CB1 and CB2 are tested in this manner. In the circuit shown in FIG. 17, the latch circuit latches the preceding test pattern, which continues to be given to the input terminals Il and I2 of the circuit blocks CB1 and CB2, so that even if the values of the latch circuits L1 and L2 change during scan operation, the internal states of the circuit blocks CB1 and CB2 remain unchanged, making the scan test possible.
In addition, in the above example, asynchronous circuits have been employed as the circuit blocks CB1 and CB2 and the circuit shown in FIG. 16 has been used as a corresponding scan test circuit. However, if synchronous circuits are employed as the scan test circuits, the third latch circuit L3 shown in FIG. 16 becomes unnecessary.
FIGS. 20 and 21 are block diagrams showing scan test circuits wherein synchronous circuits are employed as circuit blocks to be tested. In the example shown in FIG. 20, the latch L3 and the input terminal T3 for receiving the clock signal shown in FIG. 16 are omitted, and the input of the inverter 3 is connected to the input of the inverter 5. In the example shown in FIG. 21, not only the latch circuit L3 and input terminal T3 but also the inverter 3 is omitted, and the output of the inverter 4 is connected to the output terminal DO. In addition, in the scan test circuits shown in FIGS. 20 and 21, the dummy pattern described above is required.
Since the conventional test scan circuit is arranged in the manner described above, when the scan test of the circuit blocks CB1 and CB2 is to be made, there are scan test circuits which are unnecessary in this test. For example, when it is desired to test only the circuit block CB1, the scan test circuits SRL1 through SRL4 would have only to be operated; actually, however, the scan test circuits SRL5 and SRL6 also have to be shifted. Therefore, dummy data which are unnecessary in the scan operation during test have to be scanned in at the same time. This means that an amount of dummy data corresponding to one scan clock period is required for the scan test circuit SRL1. Thus, for the overall scan operation, a large amount of test time is wasted.